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You are watching: 3 bit synchronous counter using d flip flop

These types of counters autumn under the classification of synchronous controller counter.Here the mode regulate input is offered to decision whether which sequence will be generated by the counter.In this case, mode manage input is used to decision whether the respond to will execute up count or under counting.Designing of together a respond to is the exact same as developing a synchronous counter however the extra combinational logic for mode control input is required.

**Steps to architecture Synchronous 3 little Up/Down Counter**:

**1. Decision the number and kind of FF –**Here we space performing 3 little bit or mod-8 **Up or under counting,** for this reason 3 upper and lower reversal Flops are required, which deserve to count up to 23-1 = 7.Here T upper and lower reversal Flop is used.2. **Write excitation table of upper and lower reversal Flop –****Excitation table of T FF****3. Decision because that Mode manage input M –**When M=0 ,then the counter will execute up counting.When M=1 ,then the counter will carry out down counting.**4. Attract the state transition diagram and also circuit excitation table –**** ****State transition diagram because that 3 bit up/down counting.****5. Circuit excitation table –**The circuit excitation table to represent the existing states the the counting sequence and the following states after ~ the clock pulse is applied and input T of the flip-flops. By seeing the change between the present state and also the following state, we can discover the input values of 3 upper and lower reversal Flops utilizing the flip Flops excitation table. The table is designed follow to the compelled counting sequence. **Circuit excitation table**

If over there is a change in the calculation state the a upper and lower reversal flop (i.e. 0 to 1 or 1 to 0), climate the corresponding T value becomes 1 otherwise 0.

**6. Find a simplified equation using k map –**Here we are finding the minimal Boolean expression because that each upper and lower reversal Flop intake T using k map.

**Simplified equation because that K map**

**7. Createa circuit diagram –**The simplified expression because that Flip Flops is used to design circuit diagrams. Right here all the relationships are made according to streamlined expressions because that Flip Flops.

**3 little synchronous up/down counter.**

After every fall edge, as soon as T = 1, the output state of upper and lower reversal Flop will toggle.Initially Q3 = 0 , Q2= 0 , Q1= 0.

**Case 1 : when M=0 ,then M’= 1**T3 = M’Q2Q1 + MQ’2Q’1 = Q2Q1.T2 = M’Q1 + MQ’1= 1.Q1= Q1.T1= 1.Because T1= 1, as such FF1 calculation state toggles for every fall edge.The calculation state that FF 2 will toggle as soon as Q1 = 1 and the falling leaf of the clock pulse occurs.The output state the FF 3 will toggle only once Q2.Q1= 1 and also the falling edge of the clock pulse occurs.In this way, after every fall edge, state change takes place and also we can get our wanted counting sequence.

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**Case 2 : when M=1 ,then M’ =0**T3 = M’Q2Q1+MQ’2Q’1 = Q’2Q’1T2 = M’Q1+ MQ’1= 1.Q1= Q’1.T1= 1.Because T1= 1,therefore FF1 output state toggles for every fallout’s edge.The output state of FF 2 will toggle as soon as Q’1 = 1 and also the falling edge of the clock pulse occurs.The calculation state of FF 3 will toggle only as soon as Q’2.Q’1= 1 and the falling edge of the clock pulse occurs.In this way, after every fallout’s edge, state transition takes place and we can obtain our wanted counting sequence.